This invention generally relates to a semiconductor device and more particularly to the protective overcoat on an integrated circuit.
Typically, integrated circuits (IC) are fabricated on a semiconductor substrate, known as a chip, and the most common substrates are made of silicon. The silicon chip is usually assembled into a package which serves to provide effective enlargement of the distance or pitch between input/output contacts of the chip making it suitable for attachment to a printed circuit board, and to protect the IC from mechanical and environmental damage. Unfortunately, the package intended to provide that protection sometimes contributes to the device failure. Such is the case with some surface mount packages housing VLSI chips in which poor adhesion at the interface between chip and molding compound has caused delamination. A rapid increase in vapor pressure at the delaminated interface, resulting from moisture absorbed by the plastic, and the rapid heat of soldering the package to the printed wiring board causes failures manifested as package cracking, bond wire breakage, and other associated stress related failures.
Recently the semiconductor industry has introduced reduced package sizes, such as those with area array format versus more typical peripheral attach of the input and output (I/O) terminals to a lead frame encapsulated in molded plastic package. These area array assemblies are Chip Scale Packages (CSP)), an example of which is illustrated in FIG. 1, wire bonded or flip chip Ball Grid Array (BGA) packages, and Direct Chip attach (DCA) in which the chip is directly attached to the printed circuit board without use of an intermediate package. Often these area array assembles have solder bumps or balls 11 connected by reflowing the solder from the input/output (I/O) contacts of the chip to a substrate or to the Printed Circuit (PC) Board, making both electrical and mechanical connections. Because the materials of the silicon chip 10 and the substrates or PC board 12 have different coefficients of thermal expansion (CTE), stresses are introduced in the solder connection between the rigid, lower CTE chip and the more compliant, higher CTE PC board. Stresses caused by the thermal expansion mismatch occur during solder reflow, and/or as power to the IC is cycled on and off. The stresses frequently result in mechanical failure of one or more solder joints, and in turn cause electrical failure of the product.
In an attempt to alleviate the solder fatigue failures, and to distribute the thermally induced stresses over a larger area, a polymeric filler or xe2x80x9cunderfillxe2x80x9d encapsulant 15 is introduced in liquid form to surround the solder balls 11, and to fill the cavity between the chip or CSP 10, and the PC board 12. Typically, the underfill is dispensed near the chip edges and flows under the chip and around the solder balls by capillary action. The xe2x80x9cunderfillxe2x80x9d cures to a rigid form via time, temperature, of ultraviolet exposure, or some combination thereof.
The xe2x80x9cunderfillxe2x80x9d process has a number of drawbacks, including but not limited to the following: air pockets or voids 16 being entrapped under the device which can lead to localized stress concentrations, poor adhesion of the underfill to one or more of the surfaces encountered, and a tedious and time consuming process. The viscous underfill compound, most commonly an epoxy resin with inorganic fillers, is introduced methodically and slowly in an attempt to overcome void formation under the chip resulting from poor wetting to the protective overcoat on the chip, the substrate surface and/or the solder bumps.
Adhesion between material surfaces and the effects of poor wetting have long been studied; the controlling factors are recognized as cleanliness, surface tension, and topography, as well as the chemistry of the adherents.
The chip passivation or protective overcoat (PO) of choice for many semiconductor chip manufacturers is silicon nitride, primarily because it has been shown to provide excellent resistance to ingress of mobile ions and contaminants. However, silicon nitride does not provide active sites for adhesion and wetting, and is subject to stress levels which can lead to cracking, and delamination. Stresses vary by deposition techniques, and concerted attempts are made to control the amount of stress, and to provide compressive forces in order to avoid degradation of the chip performance and reliability.
Because of these shortcomings in silicon nitride protective overcoats, the chip manufacturer is frequently forced to apply a patterned film of polyimide atop the protective overcoat. FIGS. 2a and 2b illustrate a polyimide film 22 on a chip 20. The polyimide film 22 is applied in an attempt to provide improved adhesion to polymers used in semiconductor packaging, such as molding compounds 26 in a conventional leaded plastic molded package in FIG. 2b, or to an underfill or potting compound in other types of packages. The polyimide 22 is applied and patterned atop the silicon nitride or other thin film PO (21).
FIG. 2a provides a more detailed view of the surface topography of a chip 20 with a polyimide film 22 patterned over the protective overcoat 21. With respect to adhesion, the polyimide film may have a negative effect if it is sufficiently thick enough to leave a smooth, planar surface. The thin silicon nitride protective overcoat 21 follows the contours of the chip circuitry 24, but the thicker polyimide 22 softens the contours, making a more level surface; such a smooth surface is not ideally suited to optimum adhesion.
Further, while the elastic modulus of polyimide films is higher than typical inorganic films, the thick film coupled with higher thermal expansion does lead to stress on the wafer which can result in warping and/or delamination. Organic films, such as polyimide have neither the desirable high thermal stability, nor the greater thermal conductivity of inorganic films.
Polyimide precursors are applied in liquid form to the surface of a wafer having previously been prepared with an adhesion promoter, or alternately having such a compound included in the polyimide formulation. The polyimide must then be photopatterned. The polyimide formulation may include a photosensitive agent which allows direct patterning, or if it does not, a separate photoresist step is required. Next the film is cured or cross linked by a thermal process. Not only is the polyimide a very expensive compound, but the processing is time consuming, costly, and may negatively impact yield of good chips on the wafer.
Accordingly, a need exists in the industry for a reliable, chip protective overcoat readily wet by, and having good adhesion to polymers, such as molding and underfill compounds, an overcoat which imparts little stress on the chip circuitry, and one which is cost effective in wafer processing.
It is an object of the current invention to provide a reliable and cost effective chip protective overcoat having good adhesion between the layers, as well as good wetting and adhesion to polymeric materials used in assembly of integrated circuit chips.
It is an object of this invention to provide a manufacturing method for a protective overcoat having enhanced adhesion, and which utilize existing wafer fabrication equipment and materials.
It is further an object of this invention to provide a thermally stable chip protective overcoat which imparts only small and controllable stresses to the active circuits and metallization on the chip.
It is an object of the invention to provide a chip protective overcoat having excellent diffusion barrier properties.
It is also an object of the invention to provide an inorganic chip protective overcoat having improved thermal conductivity as compared to polymeric coatings.
The objectives of the invention are accomplished by providing a protective overcoat on an integrated circuit device including the following sequence of materials: a thin film of silicon oxide in the range of 5,000 to 10,000 angstroms thickness over the active circuit and metallization, a layer of silicon nitride, oxy-nitride or silicon carbide of about 1,000 to 5,000 angstroms thickness, and a top adhesion layer of silicon oxide in the range of 500 to 5,000 angstroms thickness. This composite overcoat is fabricated by plasma enhanced chemical vapor deposition onto silicon wafers by changing the gas compositions, and process variables in a reactor, but without additional wafer handling. Openings for input/output terminals are photopatterned and etched in the deposited overcoat layers.
The first and third layers of silicon dioxide function to control stresses imparted by the nitride, to provide excellent dielectric properties, and to allow adhesion both between the overcoat layers, and to polymers used in assembly of semiconductor devices. The second layer of a silicon nitride, carbide, or oxy-nitride film is used as a barrier against ingress of mobile ions or contaminants.